1. Field of the Invention
The present invention relates to a semiconductor device including a standard cell, and particularly to a wiring pattern structure of a standard cell suitable for microfabrication processes.
2. Description of the Prior Art
Conventionally, layouts of semiconductor integrated circuits are designed by disposing circuit elements called standard cells. A standard cell is to realize a functional block, such as an AND gate, an OR gate, and a flip-flop (FF), and has the internal wiring pattern designed in advance. In standard cell type LSI design, standard cells registered in a library are generally aligned in rows and wired using channels between the rows to realize a desired LSI.
In recent years, semiconductor production techniques made quite a progress, and microfabrication was further developed. Such microfabrication was realized by the extraordinary progress in micropattern forming techniques, such as mask processing, photolithography, and etching.
During the time when pattern sizes were sufficiently large, approximately perfect design patterns used to be successfully formed on wafers by forming a mask pattern accurate for a design pattern, transferring the mask pattern on a wafer by a projection optical system, and etching an underlying layer. The advance in pattern microfabrication, however, made it difficult to form accurate patterns in each process, and a problem arose that the final product dimensions were not same as the design.
In order to solve the problem, considering a conversion difference in each process, a process known as mask data preparation is extremely important for forming a mask pattern different from a design pattern so as to make the final product dimensions equal to the design pattern dimensions. Examples of such mask data preparation include MDP (Mask Data Processing) for modifying a mask pattern using, for example, graphical operations or a design rule checker (DRC) and OPC (Optical Proximity Correction) for correcting the optical proximity effects (OPE). Such processes appropriately correct a mask pattern to obtain desired final product dimensions.    Patent Document 1: JP9-120993 A    Patent Document 2: JP2006-235080 A    Non-Patent Document 1: Toshiya Kotani et al., “New Design and OPC Flow for Manufacturability for 45 nm Node and Beyond”, VLSI symposium 2005.
In recent years, with further advanced microfabrication, the value of k1 in a lithography process (k1=W/(NA/λ), W denotes the design pattern size, λ denotes the exposure wavelength of an exposure device, and NA denotes the numerical aperture of a lens used in the exposure device) was more reduced. Because OPE is, thus, likely to be increased more, workload for OPC is extremely increased. Even more advanced microfabrication results in insufficient correction by OPC, and the gap between a design pattern and final product dimensions is increased.
Particularly, in 45 nm or finer processing, some wiring patterns are difficult to be controlled for mask correction by OPC. That is, as shown in FIG. 10, a wire X disposed between facing ends of wires is likely to be attenuated in the sandwiched part due to light interference during exposure. There is a high risk of breaking the wire due to such attenuation, and thus the production yields of devices cannot be secured sufficiently.